1. Technical Field
The present disclosure relates to semiconductor memory devices and, more particularly, to a semiconductor memory device and a self-refresh method therefor, which is capable of controlling a self-refresh period performed through one input/output port according to the kind of operations performed through another input/output port in a multi-port semiconductor memory device.
2. Discussion of Related Art
In general, one memory cell of a DRAM (Dynamic Random Access Memory) includes one select transistor and one data storage capacitor. A DRAM is well known as a semiconductor memory device suitable for a high integration density on a semiconductor substrate. The DRAMs need to be periodically refreshed with a recharge operation performed on the DRAM cells, since charge leaks through the storage capacitor and the select transistor. That is, semiconductor memory devices such as DRAMs require a configuration of refresh control circuits and the like to control operations relating to a refresh operation.
Several methods widely used to refresh memory cells of a semiconductor memory device such as the DRAMs will be described as follows.
First, in a row address strobe (RAS) only refresh (ROR) method, only a row address strobe (RAS) signal is enabled while a column address strobe (CAS) signal is maintained at a precharge level, thereby performing the refresh operation of the cells. In the ROR method, refresh addresses should be provided from the outside to the memory device to perform the respective refresh operations, and during the respective refresh operations, address buses coupled to the memory device are not used for any other purposes.
Another refresh method, the automatic refresh method, may also be used. In the automatic refresh method, a CBR (CAS Before RAS) refresh method may be employed. Generally, when memory cells are accessed in a normal operation mode, RAS signals applied externally are enabled prior to the CAS signals being applied externally. In the automatic refresh method, however, a CAS signal is activated prior to an RAS signal, so as to recognize the refresh mode. In other words, the CAS signal becomes a low level before the RAS signal becomes a low level, thereby performing the refresh operation. In this method, refresh addresses are generated internally from a built-in refresh address counter, and an external control for the refresh address counter is not employed.
Furthermore, most of the currently used DRAMs employ a self-refresh mode to lessen the amount of current consumed in the refresh operation. A start cycle of this mode is the same as that of the automatic refresh method. In other words, when CAS and RAS signals simultaneously keep an active state, for example, a low level, during a given length of time, for example, over 100 μs; a self-refresh operation is performed. That is, data stored in all of the memory cells is read out by using a refresh timer during a given refresh period, then the data are amplified and re-stored back in the memory cells. During such a refresh operation, the general operations, such as the read and write operations are interrupted. In the self-refresh method, the refresh timer and the refresh address counter built into the DRAM automatically perform the required-refresh operation by using their own clock signals, without the assistance of any clock signals provided from the outside. This type refresh technology is disclosed in U.S. Pat. Nos. 4,809,233, 4,939,695, 4,943,960 and 5,315,557.
A semiconductor memory device performing such refresh operations may be classified into classes of a single port semiconductor memory device and a multi-port semiconductor memory device. FIG. 1 illustrates the single port semiconductor memory device.
FIG. 1 illustrates access paths of a conventional semiconductor memory device having four memory banks and a single input/output port.
Referring to FIG. 1, a conventional semiconductor memory device shown therein includes a memory array 10 having four memory banks 10a, 10b, 10c and 10d and a single input/output port 20. The input/output port 20 provides an input/output path for a command signal, an address signal, a data signal and other signals (not shown) provided between the semiconductor memory device and an external processor (not shown).
All of the memory banks 10a, 10b, 10c and 10d constituting the memory array 10 are configured to be accessed through the same input/output port 20, and the arrows shown as FIG. 1 indicate these access paths.
Thus, this conventional single port memory device is configured to access all memory banks constituting the memory array through one port. A refresh operation based on this configuration is performed by inputting command signals through one port. This conventional configuration, however, may be inadequate for high speed or high efficiency operation. A multi-port semiconductor memory device to overcome such a problem has been developed. This multi-port semiconductor memory device has the advantages of communicating through a plurality of processors and simultaneously accessing a plurality of memory cells through a plurality of input/output ports. Such a multi-port semiconductor memory device, however, has defects in its refresh operation.
FIG. 2 illustrates access paths of a dual-port semiconductor memory device in a conventional multi-port semiconductor memory device. As shown in FIG. 2, a conventional dual-port semiconductor memory device includes a memory array 110, a first input/output port 120a and a second input/output port 120b. 
Memory array 110 is divided into a plurality of different memory regions. The memory array includes four memory banks 110a, 110b, 110c and 110d, like the general semiconductor memory device. In the memory banks 110a, 110b, 110c and 110d, an A bank 110a and a B bank 110b in a first memory region 112 may be determined to be accessed only by signals input through the first input/output port 120a, and a C bank 110c and a D bank 10d in a second memory region 114 may be determined to be accessed only by signals input through the second input/output port 120b. 
In this case, read and write, refresh and precharge operations and the like for the first memory region 112 and the second memory region 114 are individually and independently performed through their respective input/output ports 120a and 120b. In other words, operation through any one input/output port is independent of and not dependent upon operation through another input/output port.
Such conventional multi-port semiconductor memory device, however, has the following problem in a refresh operation. In the multi-port semiconductor memory device, power is shared, thus, when a read/write operation is performed through one input/output port and a self-refresh operation is performed through another input/output port; an internal power source may become unstable. When a read or write operation is progressed through one input/output port, a refresh characteristic of another input/output port may become adversely affected.